1. Field of the Invention
The present invention generally relates to an information processing apparatus capable of executing at high speed an exception demanded while performing normal instructions of a computer program. More specifically, the present invention is directed to such an information processing apparatus that the exception is executed by an exception sequencer independently provided within the information processing apparatus with respects to the normal process sequencer.
2. Description of the Prior Art
In accordance with great progress in recent LSI techniques, many types of microprocessors with high performance (namely, information processing apparatuses) have been developed in which high processing capabilities are integrated within a single semiconductor chip. A typical information processing apparatus is so arranged as shown in FIG. 1. This conventional information processing apparatus is mainly constructed of an execution control unit 510, a data path 520, a memory control unit 530 and an instruction queue 540. In the information processing apparatus shown in FIG. 1, the execution control unit 510 corresponds to a sequencer for receiving an instruction from the instruction queue 540 to decode this instruction and therefore for performing an instructed calculation by controlling the data path 520. The execution control unit 510 is constructed of either a microprogram, or PLA and the like. Furthermore, when an instruction requiring a memory access is executed, the execution control unit 510 performs a handshake operation to access memories (not shown) via a memory data bus 20 and a memory address bus 40 under control of the memory control unit 530. The execution control unit 510 investigates whether or not any exception demand such as interrupt request at a time instant when the execution of the normal instructions is accomplished, and performs a transition process required to execute the exception (namely, transition to exception) if the exception demand is issued.
FIG. 2 is a timing chart for explaining the process operations of the normal instructions and also the exception demand, which are executed in the microprocessor shown in FIG. 1. As seen from this timing chart, both an instruction fetch operation to fetch the instruction from the memory (not shown) so as to store this instruction into the instruction queue 540, and an instruction execution operation are performed in an overlap condition. It is now assumed that an interrupt demand (i.e., exception demand) is issued while executing an instruction "B". Since the execution control unit 510 may recognize the issuance of this exception demand (or, the interrupt demand) at the end of accomplishing the instruction, recognition by the execution control unit 510 can be made after the above instruction "B" has been performed. Upon recognition of issuance of the interrupt demand, the execution control unit 510 of this microprocessor shown in FIG. 1 performs the transition operation to the exception.
The transition operation to the exception implies the following process operation. That is, the transition operation includes outputting of an interrupt acceptance signal to an external device; acquiring of an interrupt vector from an external device; calculating of an exception table address from an interrupt vector; accessing of an exception table; acquiring of a head address of an exception routine; starting to fetch an exception routine; and furthermore saving to a program counter and other types of registers. When these process operations are accomplished, if an instruction of the exception routine is fetched, the above-described exception is commenced. It should be noted that the instruction "X" and the instruction "Y", as shown in FIG. 2, correspond to an instruction series of the exception routine.
On the other hand, it is known from the conventional information processing apparatus that the sequencer for processing the normal instructions is commonly employed with the sequencer for processing the exception instruction within the execution control unit 510. As a result, the conventional information processing apparatus must execute the transition process for the exception and also other processes such as fetching of the exception routine, and furthermore must accomplish execution of the normal instruction under execution when the interrupt demand is issued until the exception is actually commenced since such an interrupt demand has been made.
As previously described, since a large number of process operations must be executed up to the transition for the exception upon issuance of the interrupt demand, it is practically very difficult to realize a high-speed interrupt response in the conventional information processing apparatus. In particular, if an instruction requiring a lengthy execution time period such as a dividing calculation demand is under execution in the conventional information processing apparatus upon issuance of the instruction demand, a lengthy preparing time period is necessarily needed so as to perform this interrupt demand.